User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 437 of 909 2019 Ambiq Micro, Inc.
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This register controls the pad configuration controls for PAD35 through PAD32. Writes to this register must
be unlocked by the PADKEY register.
Table 641: PADREGI Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
PAD35FNC-
SEL
PAD35STRNG
PAD35INPEN
PAD35PULL
RSVD
PAD34FNC-
SEL
PAD34STRNG
PAD34INPEN
PAD34PULL
RSVD
PAD33FNC-
SEL
PAD33STRNG
PAD33INPEN
PAD33PULL
RSVD
PAD32FNC-
SEL
PAD32STRNG
PAD32INPEN
PAD32PULL
Table 642: PADREGI Register Bits
Bit Name Reset RW Description
31:30 RSVD 0x0 RO
RESERVED
29:27 PAD35FNCSEL 0x3 RW
Pad 35 function select
ADCSE7 = 0x0 - Configure as the analog input for ADC single ended input 7
NCE35 = 0x1 - IOM/MSPI nCE group 35
UART1TX = 0x2 - Configure as the UART1 TX signal
GPIO35 = 0x3 - Configure as GPIO35
I2SDAT = 0x4 - I2S serial data output
CT27 = 0x5 - CTIMER connection 27
UA0RTS = 0x6 - Configure as the UART0 RTS output
RSVD = 0x7 - Reserved
26 PAD35STRNG 0x0 RW
Pad 35 drive strength
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
25 PAD35INPEN 0x0 RW
Pad 35 input enable
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
24 PAD35PULL 0x0 RW
Pad 35 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled
23:22 RSVD 0x0 RO
RESERVED
21:19 PAD34FNCSEL 0x3 RW
Pad 34 function select
ADCSE6 = 0x0 - Configure as the analog input for ADC single ended input 6
NCE34 = 0x1 - IOM/MSPI nCE group 34
UA1RTS = 0x2 - Configure as the UART1 RTS output
GPIO34 = 0x3 - Configure as GPIO34
CMPRF2 = 0x4 - Configure as the analog comparator reference 2 signal
UA0RTS = 0x5 - Configure as the UART0 RTS output
UART0RX = 0x6 - Configure as the UART0 RX input
PDMDATA = 0x7 - PDM serial data input