User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 436 of 909 2019 Ambiq Micro, Inc.
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11.7.2.9 PADREGI Register
Pad Configuration Register I (Pads 32-25)
OFFSET: 0x00000020
INSTANCE 0 ADDRESS: 0x40010020
13:11 PAD29FNCSEL 0x3 RW
Pad 29 function select
ADCSE1 = 0x0 - Configure as the analog input for ADC single ended input 1
NCE29 = 0x1 - IOM/MSPI nCE group 29
CT9 = 0x2 - CTIMER connection 9
GPIO29 = 0x3 - Configure as GPIO29
UA0CTS = 0x4 - Configure as the UART0 CTS input signal
UA1CTS = 0x5 - Configure as the UART1 CTS input signal
UART0RX = 0x6 - Configure as the UART0 RX input signal
PDM_DATA = 0x7 - Configure as PDM DATA input
10 PAD29STRNG 0x0 RW
Pad 29 drive strength
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
9 PAD29INPEN 0x0 RW
Pad 29 input enable
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
8 PAD29PULL 0x0 RW
Pad 29 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled
7:6 RSVD 0x0 RO
RESERVED
5:3 PAD28FNCSEL 0x3 RW
Pad 28 function select
I2S_WCLK = 0x0 - Configure as the PDM I2S Word Clock input
NCE28 = 0x1 - IOM/MSPI nCE group 28
CT7 = 0x2 - CTIMER connection 7
GPIO28 = 0x3 - Configure as GPIO28
RSVD4 = 0x4 - Reserved
M2MOSI = 0x5 - Configure as the IOMSTR2 SPI MOSI output signal
UART0TX = 0x6 - Configure as the UART0 TX output signal
RSVD7 = 0x7 - Reserved
2 PAD28STRNG 0x0 RW
Pad 28 drive strength
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
1 PAD28INPEN 0x0 RW
Pad 28 input enable
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
0 PAD28PULL 0x0 RW
Pad 28 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled
Table 640: PADREGH Register Bits
Bit Name Reset RW Description