User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 435 of 909 2019 Ambiq Micro, Inc.
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29:27 PAD31FNCSEL 0x3 RW
Pad 31 function select
ADCSE3 = 0x0 - Configure as the analog input for ADC single ended input 3
NCE31 = 0x1 - IOM/MSPI nCE group 31
CT13 = 0x2 - CTIMER connection 13
GPIO31 = 0x3 - Configure as GPIO31
UART0RX = 0x4 - Configure as the UART0 RX input signal
SCCCLK = 0x5 - SCARD serial clock output
RSVD = 0x6 - Reserved
UA1RTS = 0x7 - Configure as UART1 RTS output signal
26 PAD31STRNG 0x0 RW
Pad 31 drive strength
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
25 PAD31INPEN 0x0 RW
Pad 31 input enable
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
24 PAD31PULL 0x0 RW
Pad 31 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled
23:22 RSVD 0x0 RO
RESERVED
21:19 PAD30FNCSEL 0x3 RW
Pad 30 function select
ANATEST1 = 0x0 - Configure as the ANATEST1 I/O signal
NCE30 = 0x1 - IOM/MSPI nCE group 30
CT11 = 0x2 - CTIMER connection 11
GPIO30 = 0x3 - Configure as GPIO30
UART0TX = 0x4 - Configure as UART0 TX output signal
UA1RTS = 0x5 - Configure as UART1 RTS output signal
RSVD = 0x6 - Reserved
I2S_DAT = 0x7 - Configure as the PDM I2S Data output signal
18 PAD30STRNG 0x0 RW
Pad 30 drive strength
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
17 PAD30INPEN 0x0 RW
Pad 30 input enable
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
16 PAD30PULL 0x0 RW
Pad 30 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled
15:14 RSVD 0x0 RO
RESERVED
Table 640: PADREGH Register Bits
Bit Name Reset RW Description