User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 434 of 909 2019 Ambiq Micro, Inc.
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11.7.2.8 PADREGH Register
Pad Configuration Register H (Pads 28-31)
OFFSET: 0x0000001C
INSTANCE 0 ADDRESS: 0x4001001C
This register controls the pad configuration controls for PAD31 through PAD28. Writes to this register must
be unlocked by the PADKEY register.
5:3 PAD24FNCSEL 0x3 RW
Pad 24 function select
UART1TX = 0x0 - Configure as UART1 TX output signal
NCE24 = 0x1 - IOM/MSPI nCE group 24
MSPI8 = 0x2 - MSPI data connection 8
GPIO24 = 0x3 - Configure as GPIO24
UA0CTS = 0x4 - Configure as UART0 CTS input signal
CT21 = 0x5 - CTIMER connection 21
32kHzXT = 0x6 - Configure as the 32kHz crystal output signal
SWO = 0x7 - Configure as the serial trace data output signal
2 PAD24STRNG 0x0 RW
Pad 24 drive strength
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
1 PAD24INPEN 0x0 RW
Pad 24 input enable
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
0 PAD24PULL 0x0 RW
Pad 24 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled
Table 639: PADREGH Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
PAD31FNC-
SEL
PAD31STRNG
PAD31INPEN
PAD31PULL
RSVD
PAD30FNC-
SEL
PAD30STRNG
PAD30INPEN
PAD30PULL
RSVD
PAD29FNC-
SEL
PAD29STRNG
PAD29INPEN
PAD29PULL
RSVD
PAD28FNC-
SEL
PAD28STRNG
PAD28INPEN
PAD28PULL
Table 640: PADREGH Register Bits
Bit Name Reset RW Description
31:30 RSVD 0x0 RO
RESERVED
Table 638: PADREGG Register Bits
Bit Name Reset RW Description