User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 429 of 909 2019 Ambiq Micro, Inc.
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11.7.2.6 PADREGF Register
Pad Configuration Register F (Pads 20-23)
OFFSET: 0x00000014
INSTANCE 0 ADDRESS: 0x40010014
This register controls the pad configuration controls for PAD23 through PAD20. Writes to this register must
be unlocked by the PADKEY register.
5:3 PAD16FNCSEL 0x3 RW
Pad 16 function select
ADCSE0 = 0x0 - Configure as the analog ADC single ended port 0 input sig-
nal
NCE16 = 0x1 - IOM/MSPI nCE group 16
TRIG0 = 0x2 - Configure as the ADC Trigger 0 signal
GPIO16 = 0x3 - Configure as GPIO16
SCCRST = 0x4 - SCARD reset output
CMPIN0 = 0x5 - Configure as comparator input 0 signal
UART0TX = 0x6 - Configure as UART0 TX output signal
UA1RTS = 0x7 - Configure as UART1 RTS output signal
2 PAD16STRNG 0x0 RW
Pad 16 drive strength
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
1 PAD16INPEN 0x0 RW
Pad 16 input enable
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
0 PAD16PULL 0x0 RW
Pad 16 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled
Table 635: PADREGF Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
PAD23FNC-
SEL
PAD23STRNG
PAD23INPEN
PAD23PULL
RSVD
PAD22FNC-
SEL
PAD22STRNG
PAD22INPEN
PAD22PULL
RSVD
PAD21FNC-
SEL
PAD21STRNG
PAD21INPEN
PAD21PULL
RSVD
PAD20FNC-
SEL
PAD20STRNG
PAD20INPEN
PAD20PULL
Table 636: PADREGF Register Bits
Bit Name Reset RW Description
31:30 RSVD 0x0 RO
RESERVED
Table 634: PADREGE Register Bits
Bit Name Reset RW Description