User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 426 of 909 2019 Ambiq Micro, Inc.
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13:11 PAD13FNCSEL 0x3 RW
Pad 13 function select
ADCD0PSE8 = 0x0 - Configure as the ADC Differential pair 0 P, or Single
Ended input 8 analog input signal. Determination of the D0P vs SE8 usage
is done when the particular channel is selected within the ADC module
NCE13 = 0x1 - IOM/MSPI nCE group 13
CT2 = 0x2 - CTIMER connection 2
GPIO13 = 0x3 - Configure as GPIO13
I2SBCLK = 0x4 - I2C interface bit clock
UA0RTS = 0x6 - Configure as the UART0 RTS signal output
UART1RX = 0x7 - Configure as the UART1 RX input signal
10 PAD13STRNG 0x0 RW
Pad 13 drive strength
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
9 PAD13INPEN 0x0 RW
Pad 13 input enable
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
8 PAD13PULL 0x0 RW
Pad 13 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled
7:6 RSVD 0x0 RO
RESERVED
5:3 PAD12FNCSEL 0x3 RW
Pad 12 function select
ADCD0NSE9 = 0x0 - Configure as the ADC Differential pair 0 N, or Single
Ended input 9 analog input signal. Determination of the D0N vs SE9 usage
is done when the particular channel is selected within the ADC module
NCE12 = 0x1 - IOM/MSPI nCE group 12
CT0 = 0x2 - CTIMER connection 0
GPIO12 = 0x3 - Configure as GPIO12
SLnCE = 0x4 - Configure as the IOSLAVE SPI nCE signal
PDMCLK = 0x5 - PDM serial clock output
UA0CTS = 0x6 - Configure as the UART0 CTS input signal
UART1TX = 0x7 - Configure as the UART1 TX output signal
2 PAD12STRNG 0x0 RW
Pad 12 drive strength
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
1 PAD12INPEN 0x0 RW
Pad 12 input enable
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
0 PAD12PULL 0x0 RW
Pad 12 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled
Table 632: PADREGD Register Bits
Bit Name Reset RW Description