User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 424 of 909 2019 Ambiq Micro, Inc.
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11.7.2.4 PADREGD Register
Pad Configuration Register D (Pads 12-15)
OFFSET: 0x0000000C
INSTANCE 0 ADDRESS: 0x4001000C
This register controls the pad configuration controls for PAD15 through PAD12. Writes to this register must
be unlocked by the PADKEY register.
7:6 PAD8RSEL 0x0 RW
Pad 8 pullup resistor selection.
PULL1_5K = 0x0 - Pullup is ~1.5 KOhms
PULL6K = 0x1 - Pullup is ~6 KOhms
PULL12K = 0x2 - Pullup is ~12 KOhms
PULL24K = 0x3 - Pullup is ~24 KOhms
5:3 PAD8FNCSEL 0x3 RW
Pad 8 function select
M1SCL = 0x0 - Configure as the IOMSTR1 I2C SCL signal
M1SCK = 0x1 - Configure as the IOMSTR1 SPI SCK signal
NCE8 = 0x2 - IOM/MSPI nCE group 8
GPIO8 = 0x3 - Configure as GPIO8
SCCLK = 0x4 - SCARD serial clock output
RSVD5 = 0x5 - Reserved
UART1TX = 0x6 - Configure as the UART1 TX output signal
RSVD7 = 0x7 - Reserved
2 PAD8STRNG 0x0 RW
Pad 8 drive strength
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
1 PAD8INPEN 0x0 RW
Pad 8 input enable
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
0PAD8PULL 0x0RW
Pad 8 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled
Table 631: PADREGD Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
PAD15FNC-
SEL
PAD15STRNG
PAD15INPEN
PAD15PULL
RSVD
PAD14FNC-
SEL
PAD14STRNG
PAD14INPEN
PAD14PULL
RSVD
PAD13FNC-
SEL
PAD13STRNG
PAD13INPEN
PAD13PULL
RSVD
PAD12FNC-
SEL
PAD12STRNG
PAD12INPEN
PAD12PULL
Table 630: PADREGC Register Bits
Bit Name Reset RW Description