User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 419 of 909 2019 Ambiq Micro, Inc.
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11.7.2.2 PADREGB Register
Pad Configuration Register B (Pads 4-7)
OFFSET: 0x00000004
INSTANCE 0 ADDRESS: 0x40010004
This register controls the pad configuration controls for PAD7 through PAD4. Writes to this register must be
unlocked by the PADKEY register.
7:6 PAD0RSEL 0x0 RW
Pad 0 pullup resistor selection.
PULL1_5K = 0x0 - Pullup is ~1.5 KOhms
PULL6K = 0x1 - Pullup is ~6 KOhms
PULL12K = 0x2 - Pullup is ~12 KOhms
PULL24K = 0x3 - Pullup is ~24 KOhms
5:3 PAD0FNCSEL 0x3 RW
Pad 0 function select
SLSCL = 0x0 - Configure as the IOSLAVE I2C SCL signal
SLSCK = 0x1 - Configure as the IOSLAVE SPI SCK signal
CLKOUT = 0x2 - Configure as the CLKOUT signal
GPIO0 = 0x3 - Configure as GPIO0
RSVD4 = 0x4 - Reserved
MSPI4 = 0x5 - MSPI data connection 4
RSVD6 = 0x6 - Reserved
NCE0 = 0x7 - IOM/MSPI nCE group 0
2 PAD0STRNG 0x0 RW
Pad 0 drive strength
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
1 PAD0INPEN 0x0 RW
Pad 0 input enable
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
0PAD0PULL 0x0RW
Pad 0 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled
Table 627: PADREGB Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
PAD7FNCSEL
PAD7STRNG
PAD7INPEN
PAD7PULL
PAD6RSEL
PAD6FNCSEL
PAD6STRNG
PAD6INPEN
PAD6PULL
PAD5RSEL
PAD5FNCSEL
PAD5STRNG
PAD5INPEN
PAD5PULL
RSVD
PAD4FNCSEL
PAD4STRNG
PAD4INPEN
PAD4PULL
Table 626: PADREGA Register Bits
Bit Name Reset RW Description