User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 417 of 909 2019 Ambiq Micro, Inc.
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11.7.2 GPIO Registers
11.7.2.1 PADREGA Register
Pad Configuration Register A (Pads 0-3)
OFFSET: 0x00000000
INSTANCE 0 ADDRESS: 0x40010000
This register controls the pad configuration controls for PAD3 through PAD0. Writes to this register must be
unlocked by the PADKEY register.
Table 625: PADREGA Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
PAD3PWRUP
PAD3FNCSEL
PAD3STRNG
PAD3INPEN
PAD3PULL
RSVD
PAD2FNCSEL
PAD2STRNG
PAD2INPEN
PAD2PULL
PAD1RSEL
PAD1FNCSEL
PAD1STRNG
PAD1INPEN
PAD1PULL
PAD0RSEL
PAD0FNCSEL
PAD0STRNG
PAD0INPEN
PAD0PULL
Table 626: PADREGA Register Bits
Bit Name Reset RW Description
31 RSVD 0x0 RO
RESERVED
30 PAD3PWRUP 0x0 RW
Pad 3 VDD power switch enable
DIS = 0x0 - Power switch disabled
EN = 0x1 - Power switch enabled (switched to VDD)
29:27 PAD3FNCSEL 0x3 RW
Pad 3 function select
UA0RTS = 0x0 - Configure as the UART0 RTS output
SLnCE = 0x1 - Configure as the IOSLAVE SPI nCE signal
NCE3 = 0x2 - IOM/MSPI nCE group 3
GPIO3 = 0x3 - Configure as GPIO3
RSVD = 0x4 - Reserved
MSPI7 = 0x5 - MSPI data connection 7
TRIG1 = 0x6 - Configure as the ADC Trigger 1 signal
I2S_WCLK = 0x7 - Configure as the PDM I2S Word Clock input
26 PAD3STRNG 0x0 RW
Pad 3 drive strength.
LOW = 0x0 - Low drive strength
HIGH = 0x1 - High drive strength
25 PAD3INPEN 0x0 RW
Pad 3 input enable.
DIS = 0x0 - Pad input disabled
EN = 0x1 - Pad input enabled
24 PAD3PULL 0x0 RW
Pad 3 pullup enable
DIS = 0x0 - Pullup disabled
EN = 0x1 - Pullup enabled