User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 4 of 909 2019 Ambiq Micro, Inc.
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6.1.2 Main Features ................................................................................................. 178
6.2 Functional Description ............................................................................................. 179
6.2.1 Data Transfers ................................................................................................. 179
6.3 BLEIF Registers ...................................................................................................... 180
6.3.1 Register Memory Map .................................................................................... 181
6.3.2 BLEIF Registers ............................................................................................. 183
7. MSPI Master Module ....................................................................................................... 216
7.1 Functional Overview ................................................................................................ 216
7.2 Configuration ........................................................................................................... 217
7.3 PIO Operations ........................................................................................................ 217
7.3.1 Paired-Quad Device Operation (QUADCMD) ............................................... 218
7.4 DMA Operations ...................................................................................................... 219
7.5 Execute in Place (XIP) Operations .......................................................................... 220
7.5.1 XIPMM Operation .......................................................................................... 220
7.5.2 Optimized XIP Addressing ............................................................................. 220
7.5.3 Micron XIP Support ........................................................................................ 221
7.6 Command Queueing (CQ) ....................................................................................... 221
7.6.1 Command Queue Data Format ....................................................................... 221
7.6.2 CQ Interrupts .................................................................................................. 222
7.6.3 Pausing CQ Operations ................................................................................... 223
7.6.4 Using the CQ Index registers .......................................................................... 224
7.6.5 MSPI and IOM Intercommunication .............................................................. 225
7.7 Data Scrambling ...................................................................................................... 225
7.8 Auto Power Down ................................................................................................... 225
7.9 Pad Configuration and Enables ................................................................................ 225
7.9.1 Internal Pin Muxing Options ......................................................................... 226
7.9.2 MSPI Pin Timing Board/Package Considerations .......................................... 227
7.10 MSPI Registers ...................................................................................................... 228
7.10.1 Register Memory Map .................................................................................. 229
7.10.2 MSPI Registers ............................................................................................. 230
8. I2C/SPI Master Module ................................................................................................... 258
8.1 Functional Overview ................................................................................................ 258
8.1.1 Main Features ................................................................................................. 259
8.2 Functional Description ............................................................................................. 259
8.2.1 Power Control ................................................................................................. 259
8.2.2 Clocking and Resets ........................................................................................ 259
8.2.3 FIFO ................................................................................................................ 262
8.2.4 Data Alignment ............................................................................................... 262
8.2.5 Transaction Initiation ...................................................................................... 264
8.2.6 Command Queue ............................................................................................ 265
8.3 Programmer’s Reference ......................................................................................... 268
8.4 Interface Clock Generation ...................................................................................... 268
8.5 Command Operation ................................................................................................ 269
8.6 FIFO ......................................................................................................................... 270
8.7 I2C Interface ............................................................................................................ 270
8.7.1 Bus Not Busy .................................................................................................. 270