User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 378 of 909 2019 Ambiq Micro, Inc.
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10.4.2.16DMASTAT Register
DMA Status Register
OFFSET: 0x00000290
INSTANCE 0 ADDRESS: 0x50011290
DMA Status Register
19:0 LTARGADDR 0x0 RW
DMA Target Address. This register is not updated with the current address
of the DMA, but will remain static with the original address during the DMA
transfer.
Table 556: DMASTAT Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
DMAERR
DMACPL
DMATIP
Table 557: DMASTAT Register Bits
Bit Name Reset RW Description
31:3 RSVD 0x0 RO
RESERVED.
2 DMAERR 0x0 RW
DMA Error
1DMACPL 0x0RW
DMA Transfer Complete
0DMATIP 0x0RW
DMA Transfer In Progress
Table 555: DMATARGADDR Register Bits
Bit Name Reset RW Description