User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 377 of 909 2019 Ambiq Micro, Inc.
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10.4.2.14DMATOTCOUNT Register
DMA Total Transfer Count
OFFSET: 0x00000288
INSTANCE 0 ADDRESS: 0x50011288
DMA Total Transfer Count
10.4.2.15DMATARGADDR Register
DMA Target Address Register
OFFSET: 0x0000028C
INSTANCE 0 ADDRESS: 0x5001128C
DMA Target Address Register
Table 552: DMATOTCOUNT Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD TOTCOUNT
Table 553: DMATOTCOUNT Register Bits
Bit Name Reset RW Description
31:20 RSVD 0x0 RO
RESERVED.
19:0 TOTCOUNT 0x0 RW
Total Transfer Count. The transfer count must be a multiple of the THR set-
ting to avoid DMA overruns.
Table 554: DMATARGADDR Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
UTARGADDR LTARGADDR
Table 555: DMATARGADDR Register Bits
Bit Name Reset RW Description
31:20 UTARGADDR 0x100 RO
SRAM Target