User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 376 of 909 2019 Ambiq Micro, Inc.
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10.4.2.13DMACFG Register
DMA Configuration Register
OFFSET: 0x00000280
INSTANCE 0 ADDRESS: 0x50011280
DMA Configuration Register
0 DTHRSTAT 0x0 RO
Triggered DMA from FIFO reaching threshold
Table 550: DMACFG Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
DPWROFF
DAUTOHIP
DMAPRI
RSVD
DMADIR
RSVD
DMAEN
Table 551: DMACFG Register Bits
Bit Name Reset RW Description
31:11 RSVD 0x0 RO
RESERVED.
10 DPWROFF 0x0 RW
Power Off the ADC System upon DMACPL.
9DAUTOHIP 0x0RW
Raise priority to high on fifo full, and DMAPRI set to low
8 DMAPRI 0x0 RW
Sets the Priority of the DMA request
LOW = 0x0 - Low Priority (service as best effort)
HIGH = 0x1 - High Priority (service immediately)
7:3 RSVD 0x0 RO
RESERVED.
2 DMADIR 0x0 RO
Direction
P2M = 0x0 - Peripheral to Memory (SRAM) transaction. THe PDM module
will only DMA to memory.
M2P = 0x1 - Memory to Peripheral transaction. Not available for PDM mod-
ule
1 RSVD 0x0 RO
RESERVED.
0 DMAEN 0x0 RW
DMA Enable
DIS = 0x0 - Disable DMA Function
EN = 0x1 - Enable DMA Function
Table 549: DMATRIGSTAT Register Bits
Bit Name Reset RW Description