User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 374 of 909 2019 Ambiq Micro, Inc.
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10.4.2.10INTSET Register
IO Master Interrupts: Set
OFFSET: 0x0000020C
INSTANCE 0 ADDRESS: 0x5001120C
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for
testing purposes).
10.4.2.11DMATRIGEN Register
DMA Trigger Enable Register
OFFSET: 0x00000240
INSTANCE 0 ADDRESS: 0x50011240
DMA Trigger Enable Register
0THR 0x0RW
This is the FIFO threshold interrupt.
Table 544: INTSET Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
DERR
DCMP
UNDFL
OVF THR
Table 545: INTSET Register Bits
Bit Name Reset RW Description
31:5 RSVD 0x0 RO
RESERVED
4DERR 0x0RW
DMA Error receieved
3 DCMP 0x0 RW
DMA completed a transfer
2 UNDFL 0x0 RW
This is the FIFO underflow interrupt.
1OVF 0x0RW
This is the FIFO overflow interrupt.
0THR 0x0RW
This is the FIFO threshold interrupt.
Table 543: INTCLR Register Bits
Bit Name Reset RW Description