User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 371 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
10.4.2.6 FIFOTHR Register
FIFO Threshold
OFFSET: 0x00000014
INSTANCE 0 ADDRESS: 0x50011014
FIFO Threshold
10.4.2.7 INTEN Register
IO Master Interrupts: Enable
OFFSET: 0x00000200
Table 534: FIFOFLUSH Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
FIFOFLUSH
Table 535: FIFOFLUSH Register Bits
Bit Name Reset RW Description
31:1 RSVD 0x0 RO
This bitfield is reserved for future use.
0 FIFOFLUSH 0x0 WO
FIFO FLUSH.
Table 536: FIFOTHR Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD FIFOTHR
Table 537: FIFOTHR Register Bits
Bit Name Reset RW Description
31:5 RSVD 0x0 RO
This bitfield is reserved for future use.
4:0 FIFOTHR 0x10 RW
FIFO Threshold value. When the FIFO count is equal to, or larger than this
value (in words), a THR interrupt is generated (if enabled)