User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 369 of 909 2019 Ambiq Micro, Inc.
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10.4.2.3 VOICESTAT Register
Voice Status Register
OFFSET: 0x00000008
INSTANCE 0 ADDRESS: 0x50011008
Voice Status Register
25:21 RSVD 0x0 RO
This bitfield is reserved for future use.
20 I2SEN 0x0 RW
I2S interface enable.
DIS = 0x0 - Disable I2S interface.
EN = 0x1 - Enable I2S interface.
19 BCLKINV 0x0 RW
I2S BCLK input inversion.
INV = 0x0 - BCLK inverted.
NORM = 0x1 - BCLK not inverted.
18 RSVD 0x0 RO
This bitfield is reserved for future use.
17 DMICKDEL 0x0 RW
PDM clock sampling delay.
0CYC = 0x0 - No delay.
1CYC = 0x1 - 1 cycle delay.
16 SELAP 0x0 RW
Select PDM input clock source.
I2S = 0x1 - Clock source from I2S BCLK.
INTERNAL = 0x0 - Clock source from internal clock generator.
15:9 RSVD 0x0 RO
This bitfield is reserved for future use.
8 PCMPACK 0x0 RW
PCM data packing enable.
DIS = 0x0 - Disable PCM packing.
EN = 0x1 - Enable PCM packing.
7:5 RSVD 0x0 RO
This bitfield is reserved for future use.
4:3 CHSET 0x1 RW
Set PCM channels.
DIS = 0x0 - Channel disabled.
LEFT = 0x1 - Mono left channel.
RIGHT = 0x2 - Mono right channel.
STEREO = 0x3 - Stereo channels.
2:0 RSVD 0x0 RO
This bitfield is reserved for future use.
Table 529: VCFG Register Bits
Bit Name Reset RW Description