User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 368 of 909 2019 Ambiq Micro, Inc.
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10.4.2.2 VCFG Register
Voice Configuration Register
OFFSET: 0x00000004
INSTANCE 0 ADDRESS: 0x50011004
Voice Configuration Register
0 PDMCOREEN 0x1 RW
Data Streaming Control.
EN = 0x1 - Enable Data Streaming.
DIS = 0x0 - Disable Data Streaming.
Table 528: VCFG Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
IOCLKEN
RSTB
PDMCLKSEL
PDMCLKEN
RSVD
I2SEN
BCLKINV
RSVD
DMICKDEL
SELAP
RSVD
PCMPACK
RSVD
CHSET
RSVD
Table 529: VCFG Register Bits
Bit Name Reset RW Description
31 IOCLKEN 0x0 RW
Enable the IO clock.
DIS = 0x0 - Disable FIFO read.
EN = 0x1 - Enable FIFO read.
30 RSTB 0x0 RW
Reset the IP core.
RESET = 0x0 - Reset the core.
NORM = 0x1 - Enable the core.
29:27 PDMCLKSEL 0x0 RW
Select the PDM input clock.
DISABLE = 0x0 - Static value.
12MHz = 0x1 - PDM clock is 12 MHz.
6MHz = 0x2 - PDM clock is 6 MHz.
3MHz = 0x3 - PDM clock is 3 MHz.
1_5MHz = 0x4 - PDM clock is 1.5 MHz.
750KHz = 0x5 - PDM clock is 750 KHz.
375KHz = 0x6 - PDM clock is 375 KHz.
187KHz = 0x7 - PDM clock is 187.5 KHz.
26 PDMCLKEN 0x0 RW
Enable the serial clock.
DIS = 0x0 - Disable serial clock.
EN = 0x1 - Enable serial clock.
Table 527: PCFG Register Bits
Bit Name Reset RW Description