User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 367 of 909 2019 Ambiq Micro, Inc.
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25:21 PGALEFT 0x0 RW
Left channel PGA gain.
P405DB = 0x1F - 40.5 db gain.
P390DB = 0x1E - 39.0 db gain.
P375DB = 0x1D - 37.5 db gain.
P360DB = 0x1C - 36.0 db gain.
P345DB = 0x1B - 34.5 db gain.
P330DB = 0x1A - 33.0 db gain.
P315DB = 0x19 - 31.5 db gain.
P300DB = 0x18 - 30.0 db gain.
P285DB = 0x17 - 28.5 db gain.
P270DB = 0x16 - 27.0 db gain.
P255DB = 0x15 - 25.5 db gain.
P240DB = 0x14 - 24.0 db gain.
P225DB = 0x13 - 22.5 db gain.
P210DB = 0x12 - 21.0 db gain.
P195DB = 0x11 - 19.5 db gain.
P180DB = 0x10 - 18.0 db gain.
P165DB = 0xF - 16.5 db gain.
P150DB = 0xE - 15.0 db gain.
P135DB = 0xD - 13.5 db gain.
P120DB = 0xC - 12.0 db gain.
P105DB = 0xB - 10.5 db gain.
P90DB = 0xA - 9.0 db gain.
P75DB = 0x9 - 7.5 db gain.
P60DB = 0x8 - 6.0 db gain.
P45DB = 0x7 - 4.5 db gain.
P30DB = 0x6 - 3.0 db gain.
P15DB = 0x5 - 1.5 db gain.
0DB = 0x4 - 0.0 db gain.
M15DB = 0x3 - -1.5 db gain.
M300DB = 0x2 - -3.0 db gain.
M45DB = 0x1 - -4.5 db gain.
M60DB = 0x0 - -6.0 db gain.
20:19 RSVD 0x0 RO
This bitfield is reserved for future use.
18:17 MCLKDIV 0x0 RW
PDM_CLK frequency divisor.
MCKDIV4 = 0x3 - Divide input clock by 4
MCKDIV3 = 0x2 - Divide input clock by 3
MCKDIV2 = 0x1 - Divide input clock by 2
MCKDIV1 = 0x0 - Divide input clock by 1
16:10 SINCRATE 0x30 RW
SINC decimation rate.
9 ADCHPD 0x1 RW
High pass filter control.
EN = 0x1 - Enable high pass filter.
DIS = 0x0 - Disable high pass filter.
8:5 HPCUTOFF 0xb RW
High pass filter coefficients.
4:2 CYCLES 0x1 RW
Number of clocks during gain-setting changes.
1SOFTMUTE 0x0RW
Soft mute control.
EN = 0x1 - Enable Soft Mute.
DIS = 0x0 - Disable Soft Mute.
Table 527: PCFG Register Bits
Bit Name Reset RW Description