User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 365 of 909 2019 Ambiq Micro, Inc.
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10.4.2 PDM Registers
10.4.2.1 PCFG Register
PDM Configuration Register
OFFSET: 0x00000000
INSTANCE 0 ADDRESS: 0x50011000
PDM Configuration Register
Table 526: PCFG Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
LRSWAP
PGARIGHT PGALEFT
RSVD
MCLKDIV
SINCRATE
ADCHPD
HPCUTOFF
CYCLES
SOFTMUTE
PDMCOREEN
Table 527: PCFG Register Bits
Bit Name Reset RW Description
31 LRSWAP 0x0 RW
Left/right channel swap.
EN = 0x1 - Swap left and right channels (FIFO Read RIGHT_LEFT).
NOSWAP = 0x0 - No channel swapping (IFO Read LEFT_RIGHT).