User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 353 of 909 2019 Ambiq Micro, Inc.
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9.14.1.2 HOST_ISR Register
Host Interrupt Status Register
OFFSET: 0x79
The host uses this register to read interrupt status.
NOTE: All bits are cleared by a write to the IOINTCLR bit of the IOINTCTL Register.
9.14.1.3 HOST_WCR Register
Host Interrupt Write-to-Clear Register
OFFSET: 0x7A
Write a 1 to a bit in this register to clear a pending interrupt.
Table 509: HOST_ISR Register
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
FUNDFLSTAT
RDERRSTAT
SWINT5STAT SWINT4STAT SWINT3STAT SWINT2STAT SWINT1STAT SWINT0STAT
Table 510: HOST_ISR Register Bits
Bit Name Reset RW Description
7 FUNDFLSTAT 0x0 RO
This bit is set by writing a 1 to bit 31 of the IOINTCTL Register, or if the
Host attempts a FIFO read when FIFOCTR is 0.
6 RDERRSTAT 0x0 RO
This bit is set by writing a 1 to bit 30 of the IOINTCTL Register, or if the
Host attempts a FIFO read when the FIFOUPD bit is a 1.
5 SWINT5STAT 0x0 RO This bit is set by writing a 1 to bit 29 of the IOINTCTL Register.
4 SWINT4STAT 0x0 RO This bit is set by writing a 1 to bit 28 of the IOINTCTL Register.
3 SWINT3STAT 0x0 RO This bit is set by writing a 1 to bit 27 of the IOINTCTL Register.
2 SWINT2STAT 0x0 RO This bit is set by writing a 1 to bit 26 of the IOINTCTL Register.
1 SWINT1STAT 0x0 RO This bit is set by writing a 1 to bit 25 of the IOINTCTL Register.
0 SWINT0STAT 0x0 RO This bit is set by writing a 1 to bit 24 of the IOINTCTL Register.
Table 511: HOST_WCR Register
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
FUNDFLWC
RDERRWC
SWINT5WC SWINT4WC SWINT3WC SWINT2WC SWINT1WC SWINT0WC