User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 352 of 909 2019 Ambiq Micro, Inc.
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9.14 Host Side Address Space and Register
9.14.1 Host Address Space and Registers
The Host of the I/O interface can access 128 bytes in the I
2
C/SPI Slave in either I
2
C or SPI mode. Offsets
0x00 to 0x77 may be directly mapped to the Direct RAM Area. The remaining eight offset locations access
hardware functions within the I
2
C/SPI Slave. The R/W indicator refers to accesses from the Host.
9.14.1.1 HOST_IER Register
Host Interrupt Enable
OFFSET: 0x78
This register enables the FIFO read interrupts.
Table 506: REGACCINTSET Register Bits
Bit Name Reset RW Description
31:0 REGACC 0x0 RW
Register access interrupts.
Table 507: HOST_IER Register
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
FUNDFLEN
RDERREN
SWINT5EN SWINT4EN SWINT3EN SWINT2EN SWINT1EN SWINT0EN
Table 508: HOST_IER Register Bits
Bit Name Reset RW Description
7 FUNDFLEN 0x0 RW If 1, enable an interrupt that triggers when the FIFO underflows
6 RDERREN 0x0 RW
If 1, enable the interrupt which occurs when the Host attempts to access
the FIFO when read access is locked
5 SWINT5EN 0x0 RW If 1, enable software interrupt 5
4 SWINT4EN 0x0 RW If 1, enable software interrupt 4
3 SWINT3EN 0x0 RW If 1, enable software interrupt 3
2 SWINT2EN 0x0 RW If 1, enable software interrupt 2
1 SWINT1EN 0x0 RW If 1, enable software interrupt 1
0 SWINT0EN 0x0 RW If 1, enable software interrupt 0