User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 346 of 909 2019 Ambiq Micro, Inc.
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9.13.2.11INTEN Register
IO Slave Interrupts: Enable
OFFSET: 0x00000200
INSTANCE 0 ADDRESS: 0x50000200
Set bits in this register to allow this module to generate the corresponding interrupt.
Table 489: GENADD Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD GADATA
Table 490: GENADD Register Bits
Bit Name Reset RW Description
31:8 RSVD 0x0 RO
RESERVED
7:0 GADATA 0x0 RO
The data supplied on the last General Address reference.
Table 491: INTEN Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
XCMPWR
XCMPWF
XCMPRR
XCMPRF
IOINTW
GENAD
FRDERR
FUNDFL
FOVFL
FSIZE
Table 492: INTEN Register Bits
Bit Name Reset RW Description
31:10 RSVD 0x0 RO
RESERVED
9XCMPWR 0x0RW
Transfer complete interrupt, write to register space.
8XCMPWF 0x0RW
Transfer complete interrupt, write to FIFO space.
7XCMPRR 0x0RW
Transfer complete interrupt, read from register space.
6XCMPRF 0x0RW
Transfer complete interrupt, read from FIFO space.