User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 345 of 909 2019 Ambiq Micro, Inc.
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9.13.2.9 IOINTCTL Register
I/O Interrupt Control
OFFSET: 0x00000120
INSTANCE 0 ADDRESS: 0x50000120
I/O Interrupt Control
9.13.2.10GENADD Register
General Address Data
OFFSET: 0x00000124
INSTANCE 0 ADDRESS: 0x50000124
General Address Data
Table 486: PRENC Register Bits
Bit Name Reset RW Description
31:5 RSVD 0x0 RO
RESERVED
4:0 PRENC 0x0 RO
These bits hold the priority encode of the REGACC interrupts.
Table 487: IOINTCTL Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
IOINTSET
RSVD
IOINTCLR
IOINT IOINTEN
Table 488: IOINTCTL Register Bits
Bit Name Reset RW Description
31:24 IOINTSET 0x0 WO
These bits set the IOINT interrupts when written with a 1.
23:17 RSVD 0x0 RO
RESERVED
16 IOINTCLR 0x0 WO
This bit clears all of the IOINT interrupts when written with a 1.
15:8 IOINT 0x0 RO
These bits read the IOINT interrupts.
7:0 IOINTEN 0x0 RO
These read-only bits indicate whether the IOINT interrupts are enabled.