User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 344 of 909 2019 Ambiq Micro, Inc.
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9.13.2.8 PRENC Register
I/O Slave Interrupt Priority Encode
OFFSET: 0x0000011C
INSTANCE 0 ADDRESS: 0x5000011C
I/O Slave Interrupt Priority Encode
Table 484: CFG Register Bits
Bit Name Reset RW Description
31 IFCEN 0x0 RW
IOSLAVE interface enable.
DIS = 0x0 - Disable the IOSLAVE
EN = 0x1 - Enable the IOSLAVE
30:20 RSVD 0x0 RO
RESERVED
19:8 I2CADDR 0x0 RW
7-bit or 10-bit I2C device address.
7:5 RSVD 0x0 RO
RESERVED
4STARTRD 0x0RW
This bit holds the cycle to initiate an I/O RAM read.
LATE = 0x0 - Initiate I/O RAM read late in each transferred byte.
EARLY = 0x1 - Initiate I/O RAM read early in each transferred byte.
3 RSVD 0x0 RO
RESERVED
2LSB 0x0RW
This bit selects the transfer bit ordering.
MSB_FIRST = 0x0 - Data is assumed to be sent and received with MSB
first.
LSB_FIRST = 0x1 - Data is assumed to be sent and received with LSB first.
1 SPOL 0x0 RW
This bit selects SPI polarity.
SPI_MODES_0_3 = 0x0 - Polarity 0, handles SPI modes 0 and 3.
SPI_MODES_1_2 = 0x1 - Polarity 1, handles SPI modes 1 and 2.
0 IFCSEL 0x0 RW
This bit selects the I/O interface.
I2C = 0x0 - Selects I2C interface for the IO Slave.
SPI = 0x1 - Selects SPI interface for the IO Slave.
Table 485: PRENC Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD PRENC