User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 333 of 909 2019 Ambiq Micro, Inc.
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The following protocol has been defined:
▪ Data transfer may be initiated only when the bus is not busy.
▪ During data transfer, the data line must remain stable whenever the clock line is high.
▪ Changes in the data line while the clock line is high will be interpreted as control signals.
A number of bus conditions have been defined (see Figure 45) and are described in the following sections.
Figure 45. Basic I
2
C Conditions
9.9.1 Bus Not Busy
Both SDA and SCL remain high.
9.9.2 Start Data Transfer
A change in the state of SDA from high to low, while SCL is high, defines the START condition. A START
condition which occurs after a previous START but before a STOP is called a RESTART condition, and
functions exactly like a normal STOP followed by a normal START.
9.9.3 Stop Data Transfer
A change in the state of SDA from low to high, while SCL is high, defines the STOP condition.
9.9.4 Data Valid
After a START condition, SDA is stable for the duration of the high period of SCL. The data on SDA may be
changed during the low period of SCL. There is one clock pulse per bit of data. Each data transfer is
initiated with a START condition and terminated with a STOP condition. The number of data bytes
transferred between the START and STOP conditions is not limited. The information is transmitted byte-
wide and each receiver acknowledges with a ninth bit.
9.9.5 Acknowledge
Each byte of eight bits is followed by one Acknowledge (ACK) bit as shown in Figure 46. This
Acknowledge bit is a low level driven onto SDA by the receiver, whereas the master generates an extra
ACK related SCL pulse. A slave receiver which is addressed is obliged to generate an Acknowledge after
the reception of each byte. Also, on a read transfer a master receiver must generate an Acknowledge after
the reception of each byte that has been clocked out of the slave transmitter. The device that
acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the
SDA line is a stable low during the high period of the Acknowledge related SCL pulse. A master receiver
must signal an end-of-data to the slave transmitter by not generating an Acknowledge (a NAK) on the last
byte that has been clocked out of the slave. In this case, the transmitter must leave the data line high to
enable the master to generate the STOP condition.
SDA
SCL
START SDA Stable
SDA may
change
STOP
Not Busy