User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 330 of 909 2019 Ambiq Micro, Inc.
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Figure 44. I
2
C/SPI Slave Module FIFO
When the host reads a byte from the FIFO, the data retrieved is pointed to by FIFOPTR, FIFOPTR is
incremented and wraps around in the FIFO Area if it reaches FIFOMAX. FIFOSIZ and FIFOCTR are each
decremented by one. The Host can read FIFOCTR and then read that many bytes without further
checking. Note that this process can continue without requiring a CPU wakeup. If the Host attempts to read
the FIFO when FIFOSIZ is 0, the FUNDFL interrupt flag is set in both the I
2
C Slave interrupt block and in
the Host interrupt block.
When FIFOSIZ drops below the configured threshold REG_IOSLAVE_FIFOTHR the FSIZE interrupt flag is
set and if enabled an interrupt is sent to the CPU which will wake it up. At that point, the CPU can move as
much data from the SRAM FIFO to the I
2
C/SPI Slave FIFO as possible in a single operation and then go
back to sleep. Since the FIFO Area can be quite large, CPU wake-ups will be very infrequent. If a write to
the FIFOCTR which would increment the value beyond 1023 occurs, the FOVFL interrupt flag is set.
When some other process, such as a sensor read, produces new data for the FIFO, the CPU will add that
data to the FIFO in SRAM, wrapping around as necessary. The REG_IOSLAVE_FIFOINC register is then
written with the number of bytes added to the FIFO, which is added to the FIFOCTR register in an atomic
fashion. In this way the Host processor can always determine how much read data is available.
The FIFO interface offset 0x7F is treated uniquely by the I
2
C/SPI Slave, in that an access to this address
does not increment the Address Pointer. This allows the Host to initiate a burst read from address 0x7F of
any length, and each read will supply the next byte in the FIFO.
9.5 Rearranging the FIFO
In normal operation the Host reads the oldest data from the FIFO, and the CPU writes new data onto the
FIFO. In some cases it is desirable to modify this process, in particular for the FIFO to provide the newest
data. The Apollo3 Blue MCU supports such operation using a special control function.
FIFO Buffer in
SRAM
Local FIFO
FIFO Area in
LRAM
FIFOPTRCur Data
FIFO Read
Data @ 0x7F
FIFOSIZ
FIFOTHR
Compare FIFO Int
Decrement on
FIFO Read
Increment on
FIFO area
Write
FIFOCTR
Decrement on
FIFO Read
Add value on write
to FIFOINC
Host Readable
at 0x7C/0x7D