User Manual

Apollo3 Blue Datasheet

DS-A3-0p9p1 Page 329 of 909 2019 Ambiq Micro, Inc.

speed software decoding, and is therefore very useful for quickly servicing the highest priority REGACC

interrupt (i.e. the one at the lowest offset address). The encoding works such that if interrupt 31 is set,

PRENC will be 0. If interrupt 31 is not set and bit 30 is set, PRENC will be 1, and so on to the point where

if bits 31-1 are not set and bit 0 is set PRENC will be 31. If no interrupts are set the value in PRENC is

indeterminate.

The final special memory space within the Direct Area is a read-only area for the I/O Host, which is from I/

O address (REG_IOSLAVE_FIFOCFG_ROBASE * 8) to (FIFOBASE * 8 – 1). I/O writes to this address

space will not change the LRAM, which allows the space to be used for returning status to the I/O Host.

ROBASE should have a minimum value of 0x0A, representing a start address of 0x50 to allow space for

special commands and burst writes in lower Direct Area space.

9.4 FIFO Area Functions

The FIFO is used to provide very efficient flow of data from the Apollo3 Blue MCU to the I/O Host

processor with minimal CPU interaction. A FIFO of up to 1023 bytes can be easily maintained by software,

with the oldest bytes residing in the LRAM FIFO Area and the newer data being held in system SRAM and

transferred to the I

C/SPI Slave on demand. Several hardware features support this operation.

Figure 44 shows the basic FIFO operation. The main FIFO is held in a buffer in SRAM, and the oldest data

in that FIFO has been transferred to the FIFO Area of the I/O Slave. The

REG_IOSLAVE_FIFOPTR_FIFOPTR register points to the next byte to be read on the I/O interface.

REG_IOSLAVE_FIFOPTR_FIFOSIZ holds the current number of valid bytes in the FIFO on the I

C/SPI

Slave, and FIFOCTR holds the total number of bytes in the FIFO. The value in REG_IOSLAVE_FIFOCTR

may be read indirectly at any time by the Host processor via the FIFOCTRUP_FIFOCTRLO registers to

determine if there is FIFO data available (and how much is currently in the FIFO). I/O Host access to the

FIFO counter is at offset 0x7C/D.

WARNING

The host read of the FIFOCTR value via FIFOCTRUP_FIFOCTRLO is not synchronized to the write clock.

So if the host read happens during a FIFOCTR update (either through a read-modify-write of FIFOCTR

possible for the count value to be out of sync, impacting the value read in either or both the upper

(FIFOCTRUP) and lower (FIFOCTRLO) bytes. This is a very rare case, but proper code would have the

host read the two registers for the FIFOCTR value multiple times until consecutive reads are the same.