User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 328 of 909 2019 Ambiq Micro, Inc.
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The REGACCINTSTAT register provides status of the 32 individual write interrupts. If an interrupt is
enabled and set, it shows as a high bit in this register. The highest priority REGACC bit is bit 31 (set on
access to address 0x00), and the lowest priority is bit 0 (set on access to address 0x4F). The 5-bit
REG_IOSLAVE_PRENC register provides an encoded value of the highest priority of these interrupts to
Table 468: Mapping of Direct Area Access Interrupts and Corresponding REGACCINTSTAT Bits
REGACCINTSTAT Bit Direct Area Offset Address
31 0x0
30 0x1
29 0x2
28 0x3
27 0x4
26 0x5
25 0x6
24 0x7
23 0x8
22 0x9
21 0xA
20 0xB
19 0xC
18 0xD
17 0xE
16 0xF
15 0x13
14 0x17
13 0x1B
12 0x1F
11 0x23
10 0x27
90x2B
80x2F
70x33
60x37
50x3B
40x3F
30x43
20x47
10x4B
00x4F