User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 326 of 909 2019 Ambiq Micro, Inc.
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resents the start of the FIFO Area and, in so doing, defines the size of the Direct Area in 8-byte
segments. Part of this area can be defined as IO Slave Read-only starting at any 8-byte segment
defined by REG_IOSLAVE_FIFOCFG_ROBASE and extending through the end of the Direct Area
at FIFOBASE*8-1.
2. A FIFO Area which is used to stream data from the Apollo3 Blue MCU. This memory is directly
addressed from the AHB, but accessed from the I/O Interface using a single I/O address 0x7F as a
streaming port. The FIFO area is from the LRAM address calculated from the value in the
FIFOBASE field, FIFOBASE*8, to the LRAM address calculated from the value in the FIFOMAX
field of the FIFOCFG register, REG_IOSLAVE_FIFOCFG_FIFOMAX.The upper FIFO Area
address is FIFOMAX*8-1. The maximum value for FIFOMAX is 0x20, which would result in an
upper FIFO Area address of 0xFF.
3. A RAM Area which is accessible only from the AHB Slave. The RAM area is from the LRAM
address calculated from the value in the FIFOMAX field of the FIFOCFG register, REG_IO-
SLAVE_FIFOCFG_FIFOMAX, to address 0xFF. Setting FIFOMAX to 0x20 would result in a RAM
area of zero size.
The data in the LRAM is maintained in Deep Sleep Mode.
Figure 43 below shows the LRAM address mapping between the I/O interface and the AHB.
Figure 43. I
2
C/SPI Slave Module LRAM Addressing
9.3 Direct Area Functions
The Direct Area is used for direct communications between the interface Host and the Apollo3 Blue MCU.
The Host may write a register in this Register Access space, called REGACC, and read it back without
requiring the CPU to wake up, so that very low power interactions are supported. In some cases, however,
accesses require interaction with the CPU.
REGACC interrupts are mapped in the Direct Area and operate as follows. Each REGACC interrupt status
bit will be set whenever there is a read or write over the I2C or SPI interface in the Direct Area with an
offset address which corresponds to a particular REGACC interrupt. Table 468 below lists the offsets to
Up to 120 Bytes
Directly
Addressable
FIFO (Data)
0x00
0x7F
I/O Address
FIFOCTRLO0x7C
FIFOCTRUP
Direct Area
RAM/AHB
0x00
FIFO Area
RAM Area
0x7D
0xFF
IOINT Regs
FIFOBASE * 8
FIFOMAX * 8
FIFOBASE * 8 - 1
0x78-7B