User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 323 of 909 2019 Ambiq Micro, Inc.
All rights reserved.
8.15.2.35DEVCFG Register
I2C Device Configuration register
OFFSET: 0x00000404
INSTANCE 0 ADDRESS: 0x50004404
INSTANCE 1 ADDRESS: 0x50005404
INSTANCE 2 ADDRESS: 0x50006404
INSTANCE 3 ADDRESS: 0x50007404
INSTANCE 4 ADDRESS: 0x50008404
INSTANCE 5 ADDRESS: 0x50009404
Contains the I2C device address.
2 ARBEN 0x0 RW
Enables multi-master arbitration for the I2C master. If the bus is known to
have only a single master, this function can be disabled to save clock cycles
on I2C transactions
ARBEN = 0x1 - Enable multi-master bus arbitration support for this i2c mas-
ter
ARBDIS = 0x0 - Disable multi-master bus arbitration support for this i2c
master
1 I2CLSB 0x0 RW
Direction of data transmit and receive, MSB(0) or LSB(1) first. Default per
I2C specification is MSB first. This applies to both read and write data, and
read data will be bit
MSBFIRST = 0x0 - Byte data is transmitted MSB first onto the bus/read
from the bus
LSBFIRST = 0x1 - Byte data is transmitted LSB first onto the bus/read from
the bus
0 ADDRSZ 0x0 RW
Sets the I2C master device address size to either 7b (0) or 10b (1).
ADDRSZ7 = 0x0 - Use 7b addressing for I2C master transactions
ADDRSZ10 = 0x1 - Use 10b addressing for I2C master transactions
Table 464: DEVCFG Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD DEVADDR
Table 465: DEVCFG Register Bits
Bit Name Reset RW Description
31:10 RSVD 0x0 RO
Reserved
Table 463: MI2CCFG Register Bits
Bit Name Reset RW Description