User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 320 of 909 2019 Ambiq Micro, Inc.
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8.15.2.33MSPICFG Register
SPI module master configuration
OFFSET: 0x00000300
INSTANCE 0 ADDRESS: 0x50004300
INSTANCE 1 ADDRESS: 0x50005300
INSTANCE 2 ADDRESS: 0x50006300
INSTANCE 3 ADDRESS: 0x50007300
INSTANCE 4 ADDRESS: 0x50008300
INSTANCE 5 ADDRESS: 0x50009300
Controls the configuration of the SPI master module, including POL/PHA, LSB, flow control, and delays for
MISO and MOSI
0ERR 0x0RO
Bit has been deprecated. Please refer to the other error indicators. This will
always return 0.
ERROR = 0x1 - Bit has been deprecated and will always return 0.
Table 460: MSPICFG Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
MSPIRST
DOUTDLY
DINDLY
SPILSB
RDFCPOL
WTF-
WTFCIRQ
RSVD
MOSIINV
RDFC
WTFC
RSVD
FULLDUP
SPHA
SPOL
Table 461: MSPICFG Register Bits
Bit Name Reset RW Description
31 RSVD 0x0 RO
RESERVED
30 MSPIRST 0x0 RW
Not used. To reset the module, toggle the SMOD_EN for the module
29:27 DOUTDLY 0x0 RW
Delay tap to use for the output signal (MOSI). This give more hold time on
the output data
26:24 DINDLY 0x0 RW
Delay tap to use for the input signal (MISO). This gives more hold time on
the input data.
Table 459: STATUS Register Bits
Bit Name Reset RW Description