User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 319 of 909 2019 Ambiq Micro, Inc.
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8.15.2.32STATUS Register
IOM Module Status Register
OFFSET: 0x000002B4
INSTANCE 0 ADDRESS: 0x500042B4
INSTANCE 1 ADDRESS: 0x500052B4
INSTANCE 2 ADDRESS: 0x500062B4
INSTANCE 3 ADDRESS: 0x500072B4
INSTANCE 4 ADDRESS: 0x500082B4
INSTANCE 5 ADDRESS: 0x500092B4
IOM Module Status Register
7:0 CQENDIDX 0x0 RW
Holds 8 bits of data that will be compared with the CQCURIX register field.
If the values match, the IDXEQ pause event will be activated, which will
cause the pausing of command quue operation if the IDXEQ bit is enabled
in CQPAUSEEN.
Table 458: STATUS Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
IDLEST
CMDACT
ERR
Table 459: STATUS Register Bits
Bit Name Reset RW Description
31:3 RSVD 0x0 RO
RESERVED
2 IDLEST 0x0 RO
indicates if the active I/O state machine is IDLE. Note - The state machine
could be in idle state due to holdoffs from data availability, or as the com-
mand gets propagated into the logic from the registers.
IDLE = 0x1 - The I/O state machine is in the idle state.
1CMDACT 0x0RO
Indicates if the active I/O Command is currently processing a transaction, or
command is complete, but the FIFO pointers are still syncronizing internally.
This bit will go high at
ACTIVE = 0x1 - An I/O command is active. Indicates the active module has
an active command and is processing this. De-asserted when the com-
mand is completed.
Table 457: CQENDIDX Register Bits
Bit Name Reset RW Description