User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 318 of 909 2019 Ambiq Micro, Inc.
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8.15.2.31CQENDIDX Register
IOM Command Queue current index value . Compared to the CQCURIDX reg contents to generate
the IDXEQ Pause event for command queue
OFFSET: 0x000002B0
INSTANCE 0 ADDRESS: 0x500042B0
INSTANCE 1 ADDRESS: 0x500052B0
INSTANCE 2 ADDRESS: 0x500062B0
INSTANCE 3 ADDRESS: 0x500072B0
INSTANCE 4 ADDRESS: 0x500082B0
INSTANCE 5 ADDRESS: 0x500092B0
End index value, targeted to be written by software to indicate the last valid register pair contained within
the command queue. Register write operations within the command queue.
Table 454: CQCURIDX Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD CQCURIDX
Table 455: CQCURIDX Register Bits
Bit Name Reset RW Description
31:8 RSVD 0x0 RO
RESERVED
7:0 CQCURIDX 0x0 RW
Holds 8 bits of data that will be compared with the CQENDIX register field.
If the values match, the IDXEQ pause event will be activated, which will
cause the pausing of command quue operation if the IDXEQ bit is enabled
in CQPAUSEEN.
Table 456: CQENDIDX Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD CQENDIDX
Table 457: CQENDIDX Register Bits
Bit Name Reset RW Description
31:8 RSVD 0x0 RO
RESERVED