User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 316 of 909 2019 Ambiq Micro, Inc.
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8.15.2.29CQPAUSEEN Register
Command Queue Pause Enable Register
OFFSET: 0x000002A8
INSTANCE 0 ADDRESS: 0x500042A8
INSTANCE 1 ADDRESS: 0x500052A8
INSTANCE 2 ADDRESS: 0x500062A8
INSTANCE 3 ADDRESS: 0x500072A8
INSTANCE 4 ADDRESS: 0x500082A8
INSTANCE 5 ADDRESS: 0x500092A8
Enables a flag to pause an active command queue operation. If a bit is '1' and the corresponding bit in the
CQFLAG register is '1', CQ processing will halt until either value is changed to '0'.
Table 452: CQPAUSEEN Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD CQPEN
Table 453: CQPAUSEEN Register Bits
Bit Name Reset RW Description
31:16 RSVD 0x0 RO
Reserved