User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 315 of 909 2019 Ambiq Micro, Inc.
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8.15.2.28CQSETCLEAR Register
Command Queue Flag Set/Clear Register
OFFSET: 0x000002A4
INSTANCE 0 ADDRESS: 0x500042A4
INSTANCE 1 ADDRESS: 0x500052A4
INSTANCE 2 ADDRESS: 0x500062A4
INSTANCE 3 ADDRESS: 0x500072A4
INSTANCE 4 ADDRESS: 0x500082A4
INSTANCE 5 ADDRESS: 0x500092A4
Set/Clear the command queue software pause flags on a per-bit basis. Contains 3 fields, allowing for
setting, clearing or toggling the value in the software flags. Priority when the same bit
Table 449: CQFLAGS Register Bits
Bit Name Reset RW Description
31:16 CQIRQMASK 0x0 RW
Mask the bits used to generate the command queue interrupt. A '1' in the bit
position will enable the pause event to trigger the interrupt, if the CQWT_int
interrupt is enabled. Bits definitions are the same as CQPAUSE
15:0 CQFLAGS 0x0 RO
Current flag status (read-only). Bits [7:0] are software controllable and bits
[15:8] are hardware status.
Table 450: CQSETCLEAR Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD CQFCLR CQFTGL CQFSET
Table 451: CQSETCLEAR Register Bits
Bit Name Reset RW Description
31:24 RSVD 0x0 RO
Reserved
23:16 CQFCLR 0x0 WO
Clear CQFlag status bits. Will clear to 0 any SWFLAG with a '1' in the corre-
sponding bit position of this field
15:8 CQFTGL 0x0 WO
Toggle the indicated bit. Will toggle the value of any SWFLAG with a '1' in
the corresponding bit position of this field
7:0 CQFSET 0x0 WO
Set CQFlag status bits. Will set to 1 the value of any SWFLAG with a '1' in
the corresponding bit position of this field