User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 311 of 909 2019 Ambiq Micro, Inc.
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8.15.2.23DMASTAT Register
DMA Status Register
OFFSET: 0x00000290
INSTANCE 0 ADDRESS: 0x50004290
INSTANCE 1 ADDRESS: 0x50005290
INSTANCE 2 ADDRESS: 0x50006290
INSTANCE 3 ADDRESS: 0x50007290
INSTANCE 4 ADDRESS: 0x50008290
INSTANCE 5 ADDRESS: 0x50009290
Status of the DMA operation currently in progress.
19:0 TARGADDR 0x0 RW
Bits [19:0] of the target byte address for source of DMA (either read or
write). The address can be any byte alignment, and does not have to be
word aligned. In cases of non-word aligned addresses, the DMA logic will
take care for ensuring only the target bytes are read/written.
Table 440: DMASTAT Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
DMAERR
DMACPL
DMATIP
Table 441: DMASTAT Register Bits
Bit Name Reset RW Description
31:3 RSVD 0x0 RO
RESERVED.
2 DMAERR 0x0 RW
DMA Error. This active high bit signals an error was encountered during the
DMA operation. The bit can be cleared by writing to 0. Once set, this bit will
remain set until cleared by software.
1DMACPL 0x0RW
DMA Transfer Complete. This signals the end of the DMA operation. This
bit can be cleared by writing to 0, and will also be cleared when a new DMA
is started.
0DMATIP 0x0RO
DMA Transfer In Progress indicator. 1 will indicate that a DMA transfer is
active. The DMA transfer may be waiting on data, transferring data, or wait-
ing for priority.
Table 439: DMATARGADDR Register Bits
Bit Name Reset RW Description