User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 308 of 909 2019 Ambiq Micro, Inc.
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8.15.2.20DMACFG Register
DMA Configuration Register
OFFSET: 0x00000280
INSTANCE 0 ADDRESS: 0x50004280
INSTANCE 1 ADDRESS: 0x50005280
INSTANCE 2 ADDRESS: 0x50006280
INSTANCE 3 ADDRESS: 0x50007280
INSTANCE 4 ADDRESS: 0x50008280
INSTANCE 5 ADDRESS: 0x50009280
Configuration control of the DMA process, including the direction of DMA, and enablement of DMA
2DTOTCMP 0x0RO
DMA triggered when DCMDCMP = 0, and the amount of data in the FIFO
was enough to complete the DMA operation (greater than or equal to cur-
rent TOTCOUNT) when the command completed. This trigger is default
active when the DCMDCMP trigger is
1DTHR 0x0RO
Triggered DMA from THR event. Bit is read only and can be cleared by dis-
abling the DTHR trigger enable or by disabling DMA.
0 DCMDCMP 0x0 RO
Triggered DMA from Command complete event. Bit is read only and can
be cleared by disabling the DCMDCMP trigger enable or by disabling DMA.
Table 434: DMACFG Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
DPWROFF
DMAPRI
RSVD
DMADIR
DMAEN
Table 435: DMACFG Register Bits
Bit Name Reset RW Description
31:10 RSVD 0x0 RO
RESERVED.
9DPWROFF 0x0RW
Power off module after DMA is complete. If this bit is active, the module will
request to power off the supply it is attached to. If there are other units still
requiring power from the same domain, power down will not be performed.
DIS = 0x0 - Power off disabled
EN = 0x1 - Power off enabled
Table 433: DMATRIGSTAT Register Bits
Bit Name Reset RW Description