User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 307 of 909 2019 Ambiq Micro, Inc.
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8.15.2.19DMATRIGSTAT Register
DMA Trigger Status Register
OFFSET: 0x00000244
INSTANCE 0 ADDRESS: 0x50004244
INSTANCE 1 ADDRESS: 0x50005244
INSTANCE 2 ADDRESS: 0x50006244
INSTANCE 3 ADDRESS: 0x50007244
INSTANCE 4 ADDRESS: 0x50008244
INSTANCE 5 ADDRESS: 0x50009244
Provides the status of trigger events that have occurred for the transaction. Some of the bits are read only
and some can be reset via a write of 0.
Table 431: DMATRIGEN Register Bits
Bit Name Reset RW Description
31:2 RSVD 0x0 RO
RESERVED.
1 DTHREN 0x0 RW
Trigger DMA upon THR level reached. For M2P DMA operations (IOM
writes), the trigger will assert when the write FIFO has (WTHR/4) number of
words free in the write FIFO, and will transfer (WTHR/4) number of words
0 DCMDCMPEN 0x0 RW
Trigger DMA upon command complete. Enables the trigger of the DMA
when a command is completed. When this event is triggered, the number of
words transferred will be the lesser of the remaining TOTCOUNT bytes, or
Table 432: DMATRIGSTAT Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
DTOTCMP
DTHR
DCMDCMP
Table 433: DMATRIGSTAT Register Bits
Bit Name Reset RW Description
31:3 RSVD 0x0 RO
RESERVED.