User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 306 of 909 2019 Ambiq Micro, Inc.
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8.15.2.18DMATRIGEN Register
DMA Trigger Enable Register
OFFSET: 0x00000240
INSTANCE 0 ADDRESS: 0x50004240
INSTANCE 1 ADDRESS: 0x50005240
INSTANCE 2 ADDRESS: 0x50006240
INSTANCE 3 ADDRESS: 0x50007240
INSTANCE 4 ADDRESS: 0x50008240
INSTANCE 5 ADDRESS: 0x50009240
Provides control on which event will trigger the DMA transfer after the DMA operation is setup and
enabled. The trigger event will cause a number of bytes (depending on trigger event) to be
Table 429: CMDSTAT Register Bits
Bit Name Reset RW Description
31:20 RSRVD0 0x0 RO
Reserved
19:8 CTSIZE 0x0 RO
The current number of bytes still to be transferred with this command. This
field will count down to zero.
7:5 CMDSTAT 0x0 RO
The current status of the command execution.
ERR = 0x1 - Error encountered with command
ACTIVE = 0x2 - Actively processing command
IDLE = 0x4 - Idle state, no active command, no error
WAIT = 0x6 - Command in progress, but waiting on data from host
4:0 CCMD 0x0 RO
current command that is being executed
Table 430: DMATRIGEN Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
DTHREN
DCMDCMPEN