User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 304 of 909 2019 Ambiq Micro, Inc.
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8.15.2.16OFFSETHI Register
High order 2 bytes of 3 byte offset for IO transaction
OFFSET: 0x00000220
INSTANCE 0 ADDRESS: 0x50004220
INSTANCE 1 ADDRESS: 0x50005220
INSTANCE 2 ADDRESS: 0x50006220
INSTANCE 3 ADDRESS: 0x50007220
INSTANCE 4 ADDRESS: 0x50008220
INSTANCE 5 ADDRESS: 0x50009220
High order 2 bytes of 3 byte offset for IO transaction
Table 424: DCX Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
DCXEN
CE3OUT CE2OUT CE1OUT CE0OUT
Table 425: DCX Register Bits
Bit Name Reset RW Description
31:5 RSVD 0x0 RO
RESERVED
4 DCXEN 0x0 RW
Revision A: MUST NOT be programmed! Revision B: Bit 4: DCX Signaling
Enable via other CE signals. The selected DCX signal (unused CE pin) will
be driven low during write of offset byte, and high during transmission of
data bytes.
EN = 0x1 - Enable DCX.
DIS = 0x0 - Disable DCX.
3CE3OUT 0x0RW
Revision A: MUST NOT be programmed! Revision B: Enable DCX output
for CE3 output.
2CE2OUT 0x0RW
Revision A: MUST NOT be programmed! Revision B: Enable DCX output
for CE2 output.
1CE1OUT 0x0RW
Revision A: MUST NOT be programmed! Revision B: Enable DCX output
for CE1 output.
0CE0OUT 0x0RW
Revision A: MUST NOT be programmed! Revision B: Enable DCX output
for CE0 output.