User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 303 of 909 2019 Ambiq Micro, Inc.
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8.15.2.15DCX Register
DCX Control Register
OFFSET: 0x0000021C
INSTANCE 0 ADDRESS: 0x5000421C
INSTANCE 1 ADDRESS: 0x5000521C
INSTANCE 2 ADDRESS: 0x5000621C
INSTANCE 3 ADDRESS: 0x5000721C
INSTANCE 4 ADDRESS: 0x5000821C
INSTANCE 5 ADDRESS: 0x5000921C
Enables use of CE signals to transmit DCX level for SPI transactions. Only used in Apollo3 Revision B. For
Revision A, this register MUST NOT be programmed!
Table 423: CMD Register Bits
Bit Name Reset RW Description
31:24 OFFSETLO 0x0 RW
This register holds the low order byte of offset to be used in the transaction.
The number of offset bytes to use is set with bits 1:0 of the command.
23:22 RSRVD22 0x0 RO
Reserved
21:20 CMDSEL 0x0 RW
Command Specific selection information. Not used in Master I2C. Used as
CEn select for Master SPI transactions
19:8 TSIZE 0x0 RW
Defines the transaction size in bytes. The offset transfer is not included in
this size.
7CONT 0x0RW
Contine to hold the bus after the current transaction if set to a 1 with a new
command issued.
6:5 OFFSETCNT 0x0 RW
Number of offset bytes to use for the command - 0, 1, 2, 3 are valid selec-
tions. The second (byte 1) and third byte (byte 2) are read from the
OFFSETHI register, and the low order byte is pulled from this register in the
OFFSETLO field.
4:0 CMD 0x0 RW
Command for submodule.
WRITE = 0x1 - Write command using count of offset bytes specified in the
OFFSETCNT field
READ = 0x2 - Read command using count of offset bytes specified in the
OFFSETCNT field
TMW = 0x3 - SPI only. Test mode to do constant write operations. Useful for
debug and power measurements. Will continually send data in OFFSET
field
TMR = 0x4 - SPI Only. Test mode to do constant read operations. Useful for
debug and power measurements. Will continually read data from external
input