User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 300 of 909 2019 Ambiq Micro, Inc.
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8.15.2.12CLKCFG Register
I/O Clock Configuration
OFFSET: 0x00000210
INSTANCE 0 ADDRESS: 0x50004210
INSTANCE 1 ADDRESS: 0x50005210
INSTANCE 2 ADDRESS: 0x50006210
INSTANCE 3 ADDRESS: 0x50007210
INSTANCE 4 ADDRESS: 0x50008210
INSTANCE 5 ADDRESS: 0x50009210
Provides clock related controls used internal to the BLEIF module, and enablement of 32KHz clock to the
BLE Core module. The internal clock sourced is selected via the FSEL and can be further divided by 3
using the DIV3 control.
0CMDCMP 0x0RW
Command Complete interrupt. Asserted when the current operation has
completed. For repeated commands, this will only be asserted when the
final repeated command is completed.
Table 418: CLKCFG Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
TOTPER LOWPER
RSVD
DIVEN
DIV3
FSEL RSVD
IOCLKEN
Table 419: CLKCFG Register Bits
Bit Name Reset RW Description
31:24 TOTPER 0x0 RW
Clock total clock count minus 1. This provides the total period of the divided
clock -1 when the DIVEN is active. The
23:16 LOWPER 0x0 RW
Clock low clock count minus 1. This provides the number of clocks the
divided clock will be low when the DIVEN = 1.
15:13 RSVD 0x0 RO
RESERVED
12 DIVEN 0x0 RW
Enable clock division by TOTPER and LOWPER
DIS = 0x0 - Disable TOTPER division.
EN = 0x1 - Enable TOTPER division.
Table 417: INTSET Register Bits
Bit Name Reset RW Description