User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 3 of 909 2019 Ambiq Micro, Inc.
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Table of Content
1. Apollo3 Blue MCU Package Pins ..................................................................................... 47
1.1 Pin Configuration ....................................................................................................... 47
1.2 Pin Connections ......................................................................................................... 48
2. System Core ....................................................................................................................... 66
3. MCU Core Details ............................................................................................................. 68
3.1 Interrupts .................................................................................................................... 68
3.2 Memory Map ............................................................................................................. 71
3.3 Memory Protection Unit (MPU) ................................................................................ 73
3.4 System Busses ............................................................................................................ 74
3.5 Power Management ................................................................................................... 74
3.5.1 Cortex-M4 Power Modes .................................................................................. 74
3.5.2 System Power Modes ........................................................................................ 75
3.5.3 Power Control ................................................................................................... 77
3.6 Debug Interfaces ........................................................................................................ 94
3.6.1 Debugger Attachment ....................................................................................... 94
3.6.2 Instrumentation Trace Macrocell (ITM) ........................................................... 94
3.6.3 Trace Port Interface Unit (TPIU) ...................................................................... 94
3.6.4 Faulting Address Trapping Hardware ............................................................... 94
3.7 ITM Registers ............................................................................................................ 94
3.7.1 Register Memory Map ...................................................................................... 95
3.7.2 ITM Registers ................................................................................................... 97
3.8 MCUCTRL Registers .............................................................................................. 122
3.8.1 Register Memory Map .................................................................................... 123
3.8.2 MCUCTRL Registers ..................................................................................... 125
3.9 Memory Subsystem ................................................................................................. 154
3.9.1 Features ........................................................................................................... 155
3.9.2 Functional Overview ....................................................................................... 156
3.9.3 Flash Cache ..................................................................................................... 157
3.9.4 SRAM Interface .............................................................................................. 171
4. Security ............................................................................................................................ 173
4.1 Functional Overview ................................................................................................ 173
4.2 Secure Boot .............................................................................................................. 173
4.3 Secure OTA ............................................................................................................. 174
4.4 Secure Key Storage .................................................................................................. 174
4.5 External Flash Inline Encrypt/Decrypt .................................................................... 174
5. DMA ................................................................................................................................ 176
5.1 Functional Overview ................................................................................................ 176
5.1.1 General Usage ................................................................................................. 176
5.1.2 Auto Power Down .......................................................................................... 177
5.1.3 Priority ............................................................................................................ 177
5.1.4 Hardware Handshake / Hardware Triggering ................................................. 177
6. BLE Module .................................................................................................................... 178
6.1 Functional Overview ................................................................................................ 178
6.1.1 Introduction ..................................................................................................... 178