User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 298 of 909 2019 Ambiq Micro, Inc.
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8.15.2.11INTSET Register
IO Master Interrupts: Set
OFFSET: 0x0000020C
INSTANCE 0 ADDRESS: 0x5000420C
INSTANCE 1 ADDRESS: 0x5000520C
INSTANCE 2 ADDRESS: 0x5000620C
INSTANCE 3 ADDRESS: 0x5000720C
INSTANCE 4 ADDRESS: 0x5000820C
INSTANCE 5 ADDRESS: 0x5000920C
Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for
testing purposes).
5IACC 0x0RW
illegal FIFO access interrupt. Asserted when there is a overflow or under-
flow event
4NAK 0x0RW
I2C NAK interrupt. Asserted when an unexpected NAK has been received
on the I2C bus.
3FOVFL 0x0RW
Write FIFO Overflow interrupt. This occurs when software tries to write to a
full fifo. The current operation does not stop.
2 FUNDFL 0x0 RW
Read FIFO Underflow interrupt. This occurs when software tries to pop from
an empty fifo.
1THR 0x0RW
FIFO Threshold interrupt. For write operations, asserted when the number
of free bytes in the write FIFO equals or exceeds the WTHR field.
0CMDCMP 0x0RW
Command Complete interrupt. Asserted when the current operation has
completed. For repeated commands, this will only be asserted when the
final repeated command is completed.
Table 416: INTSET Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
CQERR CQUPD
CQPAUSED
DERR
DCMP
ARB
STOP
START
ICMD
IACC
NAK
FOVFL
FUNDFL
THR
CMDCMP
Table 415: INTCLR Register Bits
Bit Name Reset RW Description