User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 297 of 909 2019 Ambiq Micro, Inc.
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INSTANCE 5 ADDRESS: 0x50009208
Write a 1 to a bit in this register to clear the interrupt status associated with that bit.
Table 414: INTCLR Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
CQERR CQUPD
CQPAUSED
DERR
DCMP
ARB
STOP
START
ICMD
IACC
NAK
FOVFL
FUNDFL
THR
CMDCMP
Table 415: INTCLR Register Bits
Bit Name Reset RW Description
31:15 RSVD 0x0 RO
RESERVED
14 CQERR 0x0 RW
Error during command queue operations
13 CQUPD 0x0 RW
CQ write operation performed a register write with the register address bit 0
set to 1. The low address bits in the CQ address fields are unused and bit 0
can be used to trigger an interrupt to indicate when this register write is per-
formed by the CQ operation.
12 CQPAUSED 0x0 RO
Command queue is paused due to an active event enabled in the PAU-
SEEN register. The interrupt is posted when the event is enabled within the
PAUSEEN register, the mask is active in the CQIRQMASK field and the
event occurs.
11 DERR 0x0 RW
DMA Error encountered during the processing of the DMA command. The
DMA error could occur when the memory access specified in the DMA oper-
ation is not available or incorrectly specified.
10 DCMP 0x0 RW
DMA Complete. Processing of the DMA operation has completed and the
DMA submodule is returned into the idle state
9ARB 0x0RW
Arbitration loss interrupt. Asserted when arbitration is enabled and has been
lost to another master on the bus.
8STOP 0x0RW
STOP command interrupt. Asserted when another master on the bus has
signaled a STOP command.
7START 0x0RW
START command interrupt. Asserted when another master on the bus has
signaled a START command.
6ICMD 0x0RW
illegal command interrupt. Asserted when a command is written when an
active command is in progress.