User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 296 of 909 2019 Ambiq Micro, Inc.
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8.15.2.10INTCLR Register
IO Master Interrupts: Clear
OFFSET: 0x00000208
INSTANCE 0 ADDRESS: 0x50004208
INSTANCE 1 ADDRESS: 0x50005208
INSTANCE 2 ADDRESS: 0x50006208
INSTANCE 3 ADDRESS: 0x50007208
INSTANCE 4 ADDRESS: 0x50008208
11 DERR 0x0 RW
DMA Error encountered during the processing of the DMA command. The
DMA error could occur when the memory access specified in the DMA oper-
ation is not available or incorrectly specified.
10 DCMP 0x0 RW
DMA Complete. Processing of the DMA operation has completed and the
DMA submodule is returned into the idle state
9ARB 0x0RW
Arbitration loss interrupt. Asserted when arbitration is enabled and has been
lost to another master on the bus.
8STOP 0x0RW
STOP command interrupt. Asserted when another master on the bus has
signaled a STOP command.
7START 0x0RW
START command interrupt. Asserted when another master on the bus has
signaled a START command.
6ICMD 0x0RW
illegal command interrupt. Asserted when a command is written when an
active command is in progress.
5IACC 0x0RW
illegal FIFO access interrupt. Asserted when there is a overflow or under-
flow event
4NAK 0x0RW
I2C NAK interrupt. Asserted when an unexpected NAK has been received
on the I2C bus.
3FOVFL 0x0RW
Write FIFO Overflow interrupt. This occurs when software tries to write to a
full fifo. The current operation does not stop.
2 FUNDFL 0x0 RW
Read FIFO Underflow interrupt. This occurs when software tries to pop from
an empty fifo.
1THR 0x0RW
FIFO Threshold interrupt. For write operations, asserted when the number
of free bytes in the write FIFO equals or exceeds the WTHR field.
0CMDCMP 0x0RW
Command Complete interrupt. Asserted when the current operation has
completed. For repeated commands, this will only be asserted when the
final repeated command is completed.
Table 413: INTSTAT Register Bits
Bit Name Reset RW Description