User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 295 of 909 2019 Ambiq Micro, Inc.
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8.15.2.9 INTSTAT Register
IO Master Interrupts: Status
OFFSET: 0x00000204
INSTANCE 0 ADDRESS: 0x50004204
INSTANCE 1 ADDRESS: 0x50005204
INSTANCE 2 ADDRESS: 0x50006204
INSTANCE 3 ADDRESS: 0x50007204
INSTANCE 4 ADDRESS: 0x50008204
INSTANCE 5 ADDRESS: 0x50009204
Read bits from this register to discover the cause of a recent interrupt.
0CMDCMP 0x0RW
Command Complete interrupt. Asserted when the current operation has
completed. For repeated commands, this will only be asserted when the
final repeated command is completed.
Table 412: INTSTAT Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
CQERR CQUPD
CQPAUSED
DERR
DCMP
ARB
STOP
START
ICMD
IACC
NAK
FOVFL
FUNDFL
THR
CMDCMP
Table 413: INTSTAT Register Bits
Bit Name Reset RW Description
31:15 RSVD 0x0 RO
RESERVED
14 CQERR 0x0 RW
Error during command queue operations
13 CQUPD 0x0 RW
CQ write operation performed a register write with the register address bit 0
set to 1. The low address bits in the CQ address fields are unused and bit 0
can be used to trigger an interrupt to indicate when this register write is per-
formed by the CQ operation.
12 CQPAUSED 0x0 RO
Command queue is paused due to an active event enabled in the PAU-
SEEN register. The interrupt is posted when the event is enabled within the
PAUSEEN register, the mask is active in the CQIRQMASK field and the
event occurs.
Table 411: INTEN Register Bits
Bit Name Reset RW Description