User Manual
Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 293 of 909 2019 Ambiq Micro, Inc.
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8.15.2.8 INTEN Register
IO Master Interrupts: Enable
OFFSET: 0x00000200
INSTANCE 0 ADDRESS: 0x50004200
INSTANCE 1 ADDRESS: 0x50005200
INSTANCE 2 ADDRESS: 0x50006200
INSTANCE 3 ADDRESS: 0x50007200
INSTANCE 4 ADDRESS: 0x50008200
INSTANCE 5 ADDRESS: 0x50009200
Set bits in this register to allow this module to generate the corresponding interrupt.
Table 408: FIFOLOC Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
FIFORPTR
RSVD
FIFOWPTR
Table 409: FIFOLOC Register Bits
Bit Name Reset RW Description
31:12 RSVD 0x0 RO
Reserved
11:8 FIFORPTR 0x0 RW
Current FIFO read pointer. Used to index into the incoming FIFO (FIFO1),
which is used to store read data returned from external devices during a
read operation.
7:4 RSVD 0x0 RO
Reserved
3:0 FIFOWPTR 0x0 RW
Current FIFO write pointer. Value is the index into the outgoing FIFO
(FIFO0), which is used during write operations to external devices.
Table 410: INTEN Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSVD
CQERR
CQUPD
CQPAUSED
DERR
DCMP
ARB
STOP
START
ICMD
IACC
NAK
FOVFL
FUNDFL
THR
CMDCMP