User Manual

Apollo3 Blue Datasheet
DS-A3-0p9p1 Page 291 of 909 2019 Ambiq Micro, Inc.
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8.15.2.5 FIFOPUSH Register
FIFO PUSH register
OFFSET: 0x0000010C
INSTANCE 0 ADDRESS: 0x5000410C
INSTANCE 1 ADDRESS: 0x5000510C
INSTANCE 2 ADDRESS: 0x5000610C
INSTANCE 3 ADDRESS: 0x5000710C
INSTANCE 4 ADDRESS: 0x5000810C
INSTANCE 5 ADDRESS: 0x5000910C
Will write new data into the outgoing FIFO and advance the internal write pointer.
8.15.2.6 FIFOCTRL Register
FIFO Control Register
OFFSET: 0x00000110
INSTANCE 0 ADDRESS: 0x50004110
INSTANCE 1 ADDRESS: 0x50005110
INSTANCE 2 ADDRESS: 0x50006110
INSTANCE 3 ADDRESS: 0x50007110
Table 403: FIFOPOP Register Bits
Bit Name Reset RW Description
31:0 FIFODOUT 0x0 RW
This register will return the read data indicated by the current read pointer
on reads. If the POPWR control bit in the FIFOCTRL register is reset (0), the
fifo read pointer will be advanced by one word as a result of the read.
Table 404: FIFOPUSH Register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
FIFODIN
Table 405: FIFOPUSH Register Bits
Bit Name Reset RW Description
31:0 FIFODIN 0x0 RW
This register is used to write the FIFORAM in FIFO mode and will cause a
push event to occur to the next open slot within the FIFORAM. Writing to
this register will cause the write point to increment by 1 word(4 bytes).