User Manual

Apollo3 Blue Datasheet

DS-A3-0p9p1 Page 290 of 909 2019 Ambiq Micro, Inc.

8.15.2.4 FIFOPOP Register

FIFO POP register

OFFSET: 0x00000108

INSTANCE 0 ADDRESS: 0x50004108

INSTANCE 1 ADDRESS: 0x50005108

INSTANCE 2 ADDRESS: 0x50006108

INSTANCE 3 ADDRESS: 0x50007108

INSTANCE 4 ADDRESS: 0x50008108

INSTANCE 5 ADDRESS: 0x50009108

Will advance the internal read pointer of the incoming FIFO (FIFO1) when read, if POPWR is not active. If

POPWR is active, a write to this register is needed to advance the internal FIFO pointer.

Table 401: FIFOTHR Register Bits

Bit Name Reset RW Description

31:14 RSVD 0x0 RO

RESERVED

13:8 FIFOWTHR 0x0 RW

FIFO write threshold in bytes. A value of 0 will disable the write FIFO level

from activating the threshold interrupt. If this field is non-zero, it will trigger a

threshold interrupt when the write fifo contains FIFOWTHR free bytes, as

indicated by the FIFO0REM field. This is intended to signal when a transfer

of FIFOWTHR bytes can be done from the host to the IOM write fifo to sup-

port large IOM write operations.

7:6 RSVD 0x0 RO

RESERVED

5:0 FIFORTHR 0x0 RW

FIFO read threshold in bytes. A value of 0 will disable the read FIFO level

from activating the threshold interrupt. If this field is non-zero, it will trigger a

threshold interrupt when the read fifo contains FIFORTHR valid bytes of

data, as indicated by the FIFO1SIZ field. This is intended to signal when a

data transfer of FIFORTHR bytes can be done from the IOM module to the

host via the read fifo to support large IOM read operations.

Table 402: FIFOPOP Register

FIFODOUT